A New Opportunity for Power Savings in Mobile DRAM: Combining Deep Power-Down with Self-Refresh Mode

Today, the mobile phone has become the consumer’s favorite device, carried everywhere and never out of reach morning, noon, and night. Even so, for most users, most of the time, the mobile phone remains in a quiescent state. We spend most of the time not actively using it while powered-on. The phone rests in our pocket, on the desk, or at our bedside waiting for us to make a call, launch an app, or watch a video stream.

Thus, long periods of passive activity characterize the duty cycle of the phone’s applications processor, as the operating system and embedded radio modules tick over in the background, punctuated by short bursts of intense activity. The same pattern follows in the low-power DRAM main memory that supports the applications processor – most of the time is spent operating at a low data rate, but there are short periods of high data-rate transfers to the processor.

The JEDEC industry standard for DRAM devices does specify a power-saving feature, Partial Array Self-Refresh (PASR), which can be applied when transferring small amounts of data, to avoid refreshing the data in those latent portions of the memory array. Even so, most of the energy consumed by mobile DRAM devices is typically used at low data rates, because mobile DRAM spends so much of its time operating at these low data rates (see Figure 1).

Fig. 1: Although mobile DRAM uses less power (watts) at low data rates than at high data rates, operation at low data rates accounts for the majority of total energy consumed. (Picture credit: Winbond)
Fig. 1: Although mobile DRAM uses less power (watts) at low data rates than at high data rates, operation at low data rates accounts for the majority of total energy consumed. (Picture credit: Winbond)

There is a considerable benefit to be gained from any technology that can reduce power consumption when mobile DRAM operates at low data rates. Winbond developed a new feature that provides a dramatic extension to the power-saving capability of mobile DRAM when working at low data rates, as this article describes.

The power-saving capability of standard DRAMs

The JEDEC standard for DRAM specifies power-saving features including Automatic Temperature-Compensated Self-Refresh (ATCSR), and configurable drive strength, as well as PASR. Executing instructions in the Extended Mode Register Set (EMRS), also specified by JEDEC, deploys these features. The PASR function is applicable when the data rate is low. It operates on the principle that when the data rate transfer between the DRAM and applications processor is low, specific banks of memory cells may retain all the data in use. This feature allows the device to save the power that would have been consumed by refreshing the remaining banks because these banks contain unused data.

In a typical mobile phone use case, the operating system code, which is always in use, might be stored in one bank of a standard 256 Mbit DRAM, while the multiple other banks that are available for application data do not need refreshing when the applications are not in use. While PASR is in operation, all the internal voltage generators inside the DRAM stay in low-power mode.

It is worth noting that the operation of PASR calls for careful partitioning of the always-on data (such as operating system code) from other data types such as application data that are only required periodically.

Separately, the JEDEC standard specifies a Deep Power-Down (DPD) mode, in which the entire memory array shuts down. All internal voltage generators inside the device stop and all data is lost, as is all the information in the Mode Register Set (MRS) and the EMRS. On exit from DPD into the Active mode, the complete re-initialization process must be executed (see Figure 2). The re-initialization affects the latency of memory operations causing a delay between the call from the applications processor for a memory buffer and when the buffer becomes available.

Fig. 2: Machine state flow diagram for standard JEDEC DRAM devices showing the need to reinitialize device on exit from Deep Power-Down State (DPDS). (Picture credit: JEDEC)
Fig. 2: Machine state flow diagram for standard JEDEC DRAM devices showing the need to reinitialize device on exit from Deep Power-Down State (DPDS). (Picture credit: JEDEC)

New Winbond extended PASR mode

The power savings to be made from the PASR mode are useful but limited. Winbond offers a way to increase the power savings available from PASR by implementing a new Deep Self-Refresh (DSR) mode not specified in the JEDEC standard.

DSR operates similarly to PASR at low data rates, allocating used data to one or more banks, refreshing data, and allowing the remaining banks to lose their data by stopping the refresh current from flowing to them. With DSR, the unused banks of memory cells are allowed to go into a DPD state (see Figure 3).

 Fig. 3: Extended power saving is possible with DSR mode when seven out of eight banks of cells are allowed to enter DPD state. (Picture credit: Winbond)
Fig. 3: Extended power saving is possible with DSR mode when seven out of eight banks of cells are allowed to enter DPD state. (Picture credit: Winbond)

DPD has the advantage of reducing the total energy used in self-refresh mode even below the level achieved in PASR mode on its own (see Figure 4). The diagram illustrates the typical current drawn in PASR mode for the W948D6 device from Winbond. Fabricated in Winbond’s newest 46 nm process, the W948D6 achieves modest power savings through standard compared to power consumption when the full array is in self-refresh (IDD6) mode. While the W948D6 does not offer the new DSR mode, the 46 nm W948V6 does: the red blocks in the graph show that power falls by 40% or more compared to operation in PASR mode.

Fig. 4: Dramatic additional savings available from implementation of DSR mode.
Fig. 4: Dramatic additional savings available from implementation of DSR mode.

The new DSR mode is compatible with the JEDEC specifications, requiring only the addition of (non-standard) instructions to the EMRS. The addition of DSR capability entails no change to the hardware design and no change to the standard JEDEC pin-out. Design teams can migrate from previous DRAM architecture to a DSR-enabled DRAM such as the W948V6 without making any alterations to their board layout, and by implementing a simple additional instruction in the memory controller.
As stated above, when exiting from DPD, the memory banks need to be fully re-initialized (see Figure 5). Thus, there is some additional latency on switching from DSR to Active mode compared to the switch from PASR mode to Active mode.

Fig. 5: Machine state flow diagram showing DSR mode in addition to standard JEDEC modes.
Fig. 5: Machine state flow diagram showing DSR mode in addition to standard JEDEC modes.

Roadmap for the roll-out of DSR function

The Winbond roadmap sees the DSR function being introduced into LPDDR devices over the coming months, alongside the 256 Mbit W948V6KBHX series that is already in mass production. New devices with DSR capability will include 32 Mbit Pseudo-SRAM (PSRAM) parts in the first half of 2018 and 2 Gbit 1.8 V/1.2 V DDR2 DRAM parts in the second half of 2018. The DSR-enabled DRAM parts will be in stock in TechDesign market in a short time.

These new parts offering the DSR option will give manufacturers of mobile phones and other battery-powered devices a new means to reduce total energy use attributable to the DRAM and take advantage of additional power savings when the device is operating at a low data transfer rate.

For more Winbond mobile DRAM parts, you may visit Winbond Direct eStore on TechDesign market.

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